Sundance Catalog Sundance TV Cables SMT 348 Manuel d'utilisateur

Sundance Multiprocessor Technology Limited Form : QCF42 User Manual Date : 6 July 2006 Unit / Module Description: User Manual Unit / Module Number:

4.2 Module Description • Block1 and Block6 Xilinx Virtex 4 XC4VSX55/LX160 and configuration scheme. • Block2: QDR2 SRAM memory. • Block3: IO conn

4.2.5 FPGA Configuration schemes Different schemes are available to provide maximum flexibility in systems where the SMT348 is involved: The FPGA con

4.2.6 FPGA Reset Scheme The CPLD is connected to a TIM global Reset signal provided to the SMT348 via its primary TIM connector pin 30. (See TI TIM

Figure 2: CPLD state machine 4.2.7 FPGA Bitstream formatting If you generated you FPGA bitstream using Diamond FPGA, you do not ne

4.2.8 QDR2 SRAM Up to 4 Mbytes of QDR2 SRAM per bank. The memory is available as 4 independent banks. The QDR2 memory runs at 250MHz. Each bank is f

4.2.9 Sundance High speed Bus 2 x 60 pin connectors provide 80 IO connections between the FPGA and the outside word. They allow interfacing to other

4.2.11 TIM Connectors TIM connectors provide 4 communication links (Comports) and a Global Bus to the FPGA. The comports which are available on the S

4.2.13 Clocking scheme The SMT348 module contains a 50MHz LVTTL clock, a 200MHz clock, and a connector for an external LVTTL clock input/output. 50

As a result, check your main power supply ratings. If your system is likely to reach 25W per power rail we advice that you provide extra power to the

Device Name Quantity Voltage(V) Current(mA) Power(W) Source Samsung QDR II burst 4 (18-bit interface) V18 4 1.8 800 5.76 Samsung QDRII (-25), dat

Revision History Issue Changes Made Date Initials1.0.0 First release 06/11/06 E.P 1.0.1 Minor inconsistency about comports removed from block Di

Device Name Quantity Voltage(V) Current(mA) Power(W) Source QDRII Vref VR09 8 0.9 0 0 Samsung QDRII (-25), datasheet rev1.1 p.9XC4VLX160FF114

Details: Coolrunner XC2C256-6-CP132 power requirements based on design: Macrocells Used Pterms Used Registers Used Pins Used Function Block Inputs

5 Footprint 5.1 Top View Figure 4: Top View User Manual SMT348 Last Edited: 29/02/2008 17:52:00

5.2 Bottom View Figure 5: Bottom view User Manual SMT348 Last Edited: 29/02/2008 17:52:00

6 Pinout 6.1 FPGA Pin allocation by bank Bank I/O Vr* QDR2 SHB CP SLB GB Other Total1 48 0 2 48 0 8xConfig 8

6.4 JTAG 162534TDITCKGNDTDO3.3VTMSJP1 Figure 6: JTAG Connector, top view 7 Qualification Requirements 7.1 Qualification Tests 7.1.1 Meet Sundan

7.1.2 Speed qualification tests • QDR2 memory accesses at 250MHz. 7.1.3 Integration qualification tests • Must work on ALL Sundance platforms as

9 Physical Properties Dimensions Weight Supply Voltages Supply Current +12V +5V +3.3V -5V -12V MTBF User Manual SMT348 Last

10 Safety This module presents no hazard to the user when in normal use. User Manual SMT348 Page 28 of 29 Last Edited: 29/02/2008 17:52:00

11 EMC This module is designed to operate from within an enclosed host system, which is build to provide EMC shielding. Operation within the EU EMC

Table of Contents 1 Introduction ... 6 2

7 Qualification Requirements ...25 7.1 Qualification Tests...

Table of Figures Figure 1: Block Diagram ...9 Fig

1 Introduction The SMT348 is an FPGA TIM module designed to be integrated in modular systems. It is designed to connect to the huge range of other TI

2 Related Documents 2.1 Referenced Documents SUNDANCE SDB specification.SUNDANCE SHB specificationSUNDANCE SLB specificationSamsung QDRII Datasheet

3 Acronyms, Abbreviations and Definitions 3.1 Acronyms and Abbreviations TIM Texas Instruments Module TI© DSP Texas Instrument Digital Signal Pro

4 Functional Description This module conforms to the TIM standard (Texas Instrument Module, See TI TIM specification & user’s guide) for single