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4.2.5 FPGA Configuration schemes
Different schemes are available to provide maximum flexibility in systems where the SMT348
is involved:
The FPGA configuration bitstream source is
On Comport 3:
The CPLD is connected to the Comport 3 link of the SMT348 TIM connector. (See block1).
A switch is used to select Comport 3 as the link that will be used to receive the bitstream.
The CPLD allows for FPGA configuration in slave SelectMAP mode.
Using the on-board Flash memory.
The CPLD monitors the configuration data between the Flash and the FPGA.
The FPGA configuration is operated in Slave SelectMap mode.
A switch is used to select the Flash as the source for the configuration bitstream.
Using the on-board JTAG header and Xilinx JTAG programming tools.
The JTAG header is a Parallel-IV Header.
Note: Using JTAG to configure the FPGA bypasses the CPLD which controls configuration.
The following section describes the CPLD role and the reset scheme used.
As the CPLD is bypassed when JTAG is used to configure the FPGA, it is necessary to adopt
one of the three following ways:
If your FPGA design does not implement comport3,
o do not use the Reset signal generated by the CPLD but use the TIM reset signal
as your design’s reset. You can use JTAG to configure your FPGA with your
application and the design will reset and run everytime you issue a new TIM
reset.
If your design implements comport3
o Set the switch to configure the FPGA from flash after reset. In this way a default
bitstream being stored in flash will be loaded in the FPGA by the CPLD.
In this manner the CPLD has gone trhough the cycle of configuring the
FPGA and releases the reset (FPGAresetn)
Then you can reconfigure the FPGA via JTAG with your application.
o Set the switch to configure from comport 3. After reset, configure the FPGA via
JTAG and provide an end key word on comport 3 to the CPLD so that it releases
the Reset. (FPGAresetn).
User Manual SMT348 Page 11 of 29 Last Edited: 29/02/2008 17:52:00
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